Logical Gates (Electronics)

A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits. Logic gates are primarily implemented electronically using diodes or transistors, but can also be constructed using electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements.

In electronic logic, a logic level is represented by a voltage or current, depending on the type of electronic logic in use.

The Truth Table A truth table is a table that describes the behaviour of a logic gate or any combination of logic gates. It lists the value of the output for every possible combination of the inputs and can be used to simplify the number of logic gates and level of nesting in an electronic circuit. In general the truth table does not lead to an efficient implementation.

Different Types


All other types of Boolean logic gates (i.e., AND, OR, NOT, XOR, XNOR) can be created from a suitable network of NAND gates. Similarly all gates can be created from a network of NOR gates. Historically, NAND gates were easier to construct from MOS technology and thus NAND gates served as the first pillar of Boolean logic in electronic computation.

For an input of 2 variables, there are 16 possible boolean algebraic functions. These 16 functions are enumerated below, together with their outputs for each combination of inputs variables.
INPUT A 0 0 1 1 Meaning
B 0 1 0 1

OUTPUT FALSE 0 0 0 0 Whatever A and B, the output is false. Contradiction.
A AND B 0 0 0 1 Output is true if and only if (iff) both A and B are true.
A B 0 0 1 0 A doesn't imply B. True iff A but not B.
A 0 0 1 1 True whenever A is true.
A B 0 1 0 0 A is not implied by B. True iff not A but B.
B 0 1 0 1 True whenever B is true.
A XOR B 0 1 1 0 True iff A is not equal to B.
A OR B 0 1 1 1 True iff A is true, or B is true, or both.
A NOR B 1 0 0 0 True iff neither A nor B.
A XNOR B 1 0 0 1 True iff A is equal to B.
NOT B 1 0 1 0 True iff B is false.
A B 1 0 1 1 A is implied by B. False if not A but B, otherwise true.
NOT A 1 1 0 0 True iff A is false.
A B 1 1 0 1 A implies B. False if A but not B, otherwise true.
A NAND B 1 1 1 0 A and B are not both true.
TRUE 1 1 1 1 Whatever A and B, the output is true. Tautology.

The four functions denoted by arrows are the logical implication functions. These functions are generally less common, and are usually not implemented directly as logic gates, but rather built out of gates like AND and OR.



[b]

very lengthy ...but very nice post...keep it up.

ya..gud post... but i canot undrstnd half...

Hey guys ! Can any one tell me any two differences between RTL and TTL logic gates ?

dtl
Diode-Transistor Logic, or DTL, refers to the technology for designing and fabricating digital circuits wherein logic gates employ both diodes and transistors. DTL offers better noise margins and greater fan-outs than RTL, but suffers from low speed, especially in comparison to TTL.



RTL allows the construction of NOR gates easily, but NAND gates are relatively more difficult to get from RTL. DTL, however, allows the construction of simple NAND gates from a single transistor, with the help of several diodes and resistors.





Figure 1 shows an example of an 3-input DTL NAND gate. It consists of a single transistor Q configured as an inverter, which is driven by a current that depends on the inputs to the three input diodes D1-D3.

In the NAND gate in Figure 1, the current through diodes DA and DB will only be large enough to drive the transistor into saturation and bring the output voltage Vo to logic '0' if all the input diodes D1-D3 are 'off', which is true when the inputs to all of them are logic '1'. This is because when D1-D3 are not conducting, all the current from Vcc through R will go through DA and DB and into the base of the transistor, turning it on and pulling Vo to near ground.



However, if any of the diodes D1-D3 gets an input voltage of logic '0', it gets forward-biased and starts conducting. This conducting diode 'shunts' almost all the current away from the reverse-biased DA and DB, limiting the transistor base current. This forces the transistor to turn off, bringing up the output voltage Vo to logic '1'.



One advantage of DTL over RTL is its better noise margin. The noise margin of a logic gate for logic level '0', Δ0, is defined as the difference between the maximum input voltage that it will recognize as a '0' (Vil) and the maximum voltage that may be applied to it as a '0' (Vol of the driving gate connected to it). For logic level '1', the noise margin Δ1 is the difference between the minimum input voltage that may be applied to it as a '1' (Voh of the driving gate connected to it) and the minimum input voltage that it will recognize as a '1' (Vih). Mathematically, Δ0 = Vil-Vol and Δ1 = Voh-Vih. Any noise that causes a noise margin to be overcome will result in a '0' being erroneously read as a '1' or vice versa. In other words, noise margin is a measure of the immunity of a gate from reading an input logic level incorrectly.



In a DTL circuit, the collector output of the driving transistor is separated from the base resistor of the driven transistor by several diodes. Circuit analysis would easily show that in such an arrangement, the differences between Vil and Vol, and between Voh and Vih, are much larger than those exhibited by RTL gates, wherein the collector of the driving transistor is directly connected to the base resistor of the driven transistor. This is why DTL gates are known to have better noise margins than RTL gates.



One problem that DTL doesn't solve is its low speed, especially when the transistor is being turned off. Turning off a saturated transistor in a DTL gate requires it to first pass through the active region before going into cut-off. Cut-off, however, will not be reached until the stored charge in its base has been removed. The dissipation of the base charge takes time if there is no available path from the base to ground. This is why some DTL circuits have a base resistor that's tied to ground, but even this requires some trade-offs. Another problem with turning off the DTL output transistor is the fact that the effective capacitance of the output needs to charge up through Rc before the output voltage rises to the final logic '1' level, which also consumes a relatively large amount of time. TTL, however, solves the speed problem of DTL elegantly.



Figure 1 shows an example of an 3-input DTL NAND gate. It consists of a single transistor Q configured as an inverter, which is driven by a current that depends on the inputs to the three input diodes D1-D3.

rtl

Resistor-Transistor Logic, or RTL, refers to the obsolete technology for designing and fabricating digital circuits that employ logic gates consisting of nothing but transistors and resistors. RTL gates are now seldom used, if at all, in modern digital electronics design because it has several drawbacks, such as bulkiness, low speed, limited fan-out, and poor noise margin. A basic understanding of what RTL is, however, would be helpful to any engineer who wishes to get familiarized with TTL, which for the past many years has become widely used in digital devices such as logic gates, latches, buffers, counters, and the like.





Figure 1 shows an example of an N-input RTL NOR gate. It consists of N transistors, whose collectors are all tied up to Vcc through a common resistor, and whose emitters are all grounded. Their bases individually act as inputs for input voltages Vi (i = 1,2,...,N), which represent input logic levels. The output Vo is taken across the collector- resistor node and ground. Vo is only 'high' if the inputs to the bases of all the transistors are 'low'.

One of the earliest gates used in integrated circuits is a special type of RTL gate known as the direct-coupled transistor logic (DCTL) gate. A DCTL gate is one wherein the bases of the transistors are connected directly to inputs without any base resistors. Thus, the RTL NOR gate shown in Figure 1 becomes a DCTL NOR gate if all the base resistors (Rb's) are eliminated. Without the base resistors, DCTL gates are more economical and simpler to fabricate onto integrated circuits than RTL gates with base resistors.



The main drawback of DCTL gates is that they suffer from a phenomenon known as current hogging. Ideally, several transistors that are connected in parallel will share the load current equally among themselves when they are all brought into saturation. In the real world, however, the saturation points of different transistors are attained with different levels of input voltages to the base (Vbe). As such, transistors that are in parallel and share the same input voltage (which are commonly encountered in DCTL circuits) do not share the load current evenly among themselves.



In fact, once the transistor with the lowest Vbesat saturates, the other transistors are prevented from saturating themselves. This causes the saturated transistor to 'hog' the load current, i.e., it carries the bulk of the load current whereas those transistors that were prevented from saturating carries a minimal portion of it. Current hogging, which prevented DCTL from becoming widely used, is largely avoided in RTL circuits simply by retaining the base resistors.



RTL gates also exhibit limited 'fan-outs'. The fan-out of a gate is the ability of its output to drive several other gates. The more gates it can drive, the higher is its fan-out. The fan-out of a gate is limited by the current that its output can supply to the gate inputs connected to it when the output is at logic '1', since at this state it must be able to drive the connected input transistors into saturation.



Another weakness of an RTL gate is its poor noise margin. The noise margin of a logic gate for logic level '0', Δ0, is defined as the difference between the maximum input voltage that it will recognize as a '0' (Vil) and the maximum voltage that may be applied to it as a '0' (Vol of the driving gate connected to it). For logic level '1', the noise margin Δ1 is the difference between the minimum input voltage that may be applied to it as a '1' (Voh of the driving gate connected to it) and the minimum input voltage that it will recognize as a '1' (Vih). Mathematically, Δ0 = Vil-Vol and Δ1 = Voh-Vih. Any noise that causes a noise margin to be overcome will result in a '0' being erroneously read as a '1' or vice versa. In other words, noise margin is a measure of the immunity of a gate from reading an input logic level incorrectly.



In an RTL circuit, the collector output of the driving transistor is directly connected to the base resistor of the driven transistor. Circuit analysis would easily show that in such an arrangement, the differences between Vil and Vol, and between Voh and Vih, are not that large. This is why RTL gates are known to have poor noise margins in comparison to DTL and TTL gates.



Figure 1. A simple N-input RTL NOR Gate

+1 Reputation added. Next question I want to know is - What is the value of FAN-IN and FAN-OUT in RTL , DTL & TTL logic gates ?

brother please refer to the link below
click here

Thanx u for the link. +1 added . But still i am searching for correct answer